Imec and Synopsys are to collaborate on the 5nm node with nanowires and other devices like FinFETs, and Tunnel-FETs.
The agreement enables Synopsys to deliver process-calibrated models for its Sentaurus TCAD tools to semiconductor manufacturers for use during 5-nm technology node research and development.
This agreement follows collaborations on FinFET and 3D-IC technologies for the 10-nm and 7-nm technology nodes.
The Imec-Synopsys team is investigating, among other topics, a vertical nanowire-nanosheet hybrid SRAM cell to target 5-nm technology.
Early studies show the benefits of nanowire-nanosheet technology in density and performance compared to conventional FinFETs and lateral nanowires.
Synopsys’ Sentaurus TCAD tools that support this collaboration are used by technology development teams at foundries and integrated device manufacturers (IDMs) for device architecture selection, design and process optimization.
Using early versions of Synopsys’ TCAD models allows the Imec project team to explore a range of topics including fundamental device physics (material science, quantum transport and strain engineering), middle-of-line (MOL) local interconnects and the optimization of parasitics.
A significant part of the analysis involves full-3D process and electrical simulations to identify device and interconnect reliability solutions for these highly scaled circuits.
“This is the first time a process-calibrated TCAD simulation flow has been used to comprehensively study the process, device and circuit architectures so early in the technology path-finding process,” says Imec’s Anda Mocuta.
This simulation flow enables technologists to evaluate the speed and power consumption of ring oscillators and other test circuits in the early stage of technology development, thereby closely linking technology development and selection with circuit-level targets.
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