Analog Devices is aiming at low-power signal measurement with a combined synchronous demodulator and filter chip which allows precision magnitude and phase measurements to be made on analogue signals buried in noise.
Called ADA2200, the IC has a digitally-controlled switched-capacitor analogue signal chain, which the firm describes as ‘sampled analogue technology’ (SAT), that Analog acquired when it bought Lyric Semiconductor.
“By processing the signal entirely in the analogue domain, this analogue-in, sampled-analogue-out device reduces A/D converter sample rates, lowering A/D converter power consumption and off-loading computationally heavy tasks from the digital processor or microcontroller,” claimed Analog.
Consumption is 390uA from 3.3V (clocking at 500kHz), suiting the device to battery power. The firm see it being used for impedance measurement, gas detection, air analysis, fluid analysis, strain gauges and proximity measurement; in medical, industrial and communications markets.
Inside (see diagram) it includes a low-pass FIR (finite impulse response) filter, 1/8x decimation filter, configurable IIR (infinite impulse response) filter, a mixer with 0°/90° phase selection, reference clock and A/D converter driver output.
Optimised for input sampling rates up to 1MHz, it can demodulation input bandwidths to 30kHz with 0.009° phase detection sensitivity. Operation is from -40 to +85°C.
Synchronous detection (see diagram) is suite to sensors that have a small output in noisy environments.
Rather than stimulate the sensor with a dc voltage, it is energised by an ac reference signal. Then at the measuring end, that same ac signal is multiplied by the received sensor output. This multiplied output is the desired sensor output at DC (0Hz), plus a bunch of higher frequency rubbish that can be filtered off.
A modification in the case of the ADA2200 is that it has a divide-by-eight ‘decimation’ filter, which reduces the sampling rate needed in a subsequent ADC.
Dividers in the chip provide the ac reference signal from a master clock. In a typical application, said Analog, an 80kHz master results in the chip generating a 1.25kHz reference clock for the sensor. 80kHz clocks the input low-pass filter, and results in a sample rate of 10kHz after the decimation filter. 1.25kHz, locked to the 80kHz, is also the centre frequency of the on-chip IIR filter in its default band-pass configuration.
0 and 90degree options are available at the multiplier input to allow for phase-shifts in external circuits as synchronous detection will not work if there is exactly 90°between the reference and sensor output signals.
As the output of a synchronous detector is dependent on both the amplitude of the input and the relative phases of the reference and received signal, the chip can be used as a phase detector if the input amplitude is kept constant.
By measuring the chip output in both 0 and 90° modes, and squaring those to readings, the phase is proportional to the square root of the sum of the squares.
The 90°phase shift also enables a pair of ADA2200devices to perform in-phase and quadrature demodulation.
The output can either be read by an ADC, or used as an analogue waveform via a low-pass reconstruction filter.
When the demodulation function is disabled, the signal chain acts as a precision filter with a programmable bandwidth and tunable centre frequency. “The filter characteristics are highly stable over temperature, supply, and process variation,” said Analog.
Internal registers are programmed over an serial port, or the chip can boot itself from a serial EEPROM.
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