2019年5月15日 星期三

Mentor tools for 5nm TSMC finfet process

TSMC has certified a suite of Mentor Calibre nmPlatform design tools for its 5nm finfet process, including nmDRC, nmLVS, YieldEnhancer, PERC (pictured) and Analog FastSPICE (AFS) Platform software. “For example, Calibre PERC reliability verification solution on TSMC’s 5nm FinFET technology is engineered to help enhance product reliability by making leakage checks available for full chip designs,” said ...

This story continues at Mentor tools for 5nm TSMC finfet process

Or just read more coverage at Electronics Weekly



from News – Electronics Weekly http://bit.ly/2EaxsP7
via Yuichun

沒有留言:

張貼留言