Sidense CTO and founder Wlodek Kurjanowicz
Sidense, the Ottawa developer of NV OTP IP cores, says it has demonstrated read and write capability for its 1T-OTP bit-cell architecture on test silicon fabricated on TSMC’s 16nm CMOS finfet process.
“Sidense’s embedded one-time programmable memory macros have been licensed in customers’ designs from 0.18-micron down to 28nm and have been proven at the 20nm process node as well,” says CTO and founder, Wlodek Kurjanowicz. “Our split-channel 1T-OTP macros were designed to be highly scalable with shrinking process nodes. It is gratifying to see our theories proven in new transistor architectures such as finfet.”
Preliminary test results at 16nm confirm correct bit-cell operation with a programming voltage comparable to Sidense 1T-OTP at 28nm with 10x lower leakage current.
Programmed bit-cell characteristics are as good as or better than those for 20nm and 28nm bit cells with large margins between programmed and un-programmed cells and with excellent post-bake bit-cell stability, the company said.
Sidense provides non-volatile one-time programmable (OTP) logic non-volatile memory (LNVM) IP for use in standard-logic CMOS processes.
Its 1T cell does not require extra masks or process steps to manufacture and offer a field-programmable alternative to flash, mask ROM, eFuse and other embedded and off-chip NVM technologies for many code storage, encryption key, analog trimming and device configuration uses.
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