Renesas reduces write energy and voltage application time for STT-MRAM

At IEDM, Renesas described the development of two technologies that reduce the energy and voltage application time for the write operation of STT-MRAM. On a 20Mb test chip with embedded MRAM memory cell array in a 16 nm FinFET logic process, a 72% reduction in write energy and a 50% reduction in the voltage application ...

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