IBM beats finFETs with vertical CMOS at IEDM

IBM revealed vertical FET CMOS logic at a sub-45nm gate pitch on bulk silicon wafers at the IEEE International electron devices meeting in San Francisco this week. IBM’s VTFET with a vertical channel (yellow) and gate-all-around (blue). Contacts are brown and the white line shows current flow. It calls them VTFETs, for vertical transport FETs, and ...

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