MIPS ports hypervisor to low-end 32-bit MPU

MIPS Technologies is sourced a hypervisor for its M5150 (5-stage pipe) 32bit microcontroller, which includes hardware virtualisation.

Combining hypervisor software with virtualisation hardware, allows multiple operating systems and applications to be run on the same silicon with a significant (some claim total) cut in the risk of hacking. In phones, this pairing is used to protect, for example, banking applications.

This level of security is now looking essential for Internet-of-things applications, which is one of the markets the firm’s M-Class cores are aimed at.

Japanese firm Seltech, known for creating hypervisors for Nvidea Tegra, said MIPS, has provided a hypervisor called Fexerox for M5150.

“This accomplishment creates the framework for next-generation security solutions based on trusted execution environment (TEE) concepts defined by GlobalPlatform,” said MIPS.

It suggests applications in: wearable devices running, for example, multimedia DRM streaming, e-health data collection and in-app billing, and hardening automotive electronics against malicious attacks.

There is a video on Fexerox and MIPS M-class.

steve bush

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via Yuichun