Called DQ8051, the quad pipeline core benchmarks at 0.27292 DMips/MHz (Dhrystone 2.1) “29.01 times speed-up over the original 80C51 chip operating at the same frequency,” said the firm. “But the speed is not all. Dynamic power consumption can be as low as 1.2µW/MHz.”
In fast form, the processor core has 7,500 gates. Up to 27.297 VAX Mips are available at 100MHz.
Fully synthesizable, it is static synchronous with no internal tri-states and Technology independent – so it can be used in asics or FPGAs
Speeds range from 70MHz on a 0.35µm process up to 430MHz on 90nm – using around 10,000 gates in each case. 88% of opcodes are single instruction, average instruction 1.36cycle.
Available interfaces include: USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces.
There is also a hardware debugger with a smart trace which doesn’t capture addresses of all executed instructions, only these related to the start of tracing, conditional jumps and interrupts. Captured instructions are read back by debug software, analysed and then presented to the user as ASM code and related C lines.
DQ8051 is delivered with automated test-bench and complete set of tests, allowing package validation at each stage of SoC design flow.
In the diagram above:
- SXDM is synchronous external data memory (SXDM) interface for off-core on-die data memory to store large variables, frequently accessed by CPU, improving overall performance of application.
- DPTR are data pointers for faster memory blocks copying
- MDU32… hmm… we are guessing 32bit multiply divide unit
Memory:
- up to 256bytes of internal (on-chip) data memory
- up to 64kbyte of program memory
- up to 16Mbyte of external (off-chip) data memory – XDM
- up to 64kbyte of (on-chip) fast synchronous external data memory – SXDM
- user programmable program memory wait states – for different memories.
- user programmable external data memory wait states solution- for different memories.
- de-multiplexed address/data bus
from News http://ift.tt/1G8K4Rf
via Yuichun
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