Open standard for RISC-V verification is announced at DVCon

At this year’s (virtual) functional design and verification conference, DVCon US 2022, the RISC-V Verification Interface (RVVI) was announced by Imperas Software. The interface is available at github. The draft open standard defines “a number of interfaces required to bring together several of the subsystems required for RISC-V processor design verification”. Components based on the open ...

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