Cadence Design Systems has announced that its Allegro system-in-package (SiP) and physical verification system (PVS) implementation technologies have been enabled for TSMC's integrated fan-out (InFO) packaging technology. By providing an integrated solution that automates the design-rule checking (DRC) flow, the Allegro SiP design tools and PVS enable TSMC customers to shorten the InFO design and verification cycle.
from DIGITIMES: IT news from Asia http://ift.tt/1FtfNiH
via Yuichun
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