Memory chips must meet strict specifications for fast data transfer, reliability, and power consumption, so accurate characterization is required at every stage of design. The introduction of FinFETs at 16 and 14 nm nodes enables higher density and performance, and reduced power usage, but it also increases challenges in design and validation. Memory designers need a tool that can help them analyze parasitics quickly and accurately throughout the design cycle.
from EETimes: http://ift.tt/1Apuz7O
via Yuichun
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