Compared with generation two, they have a faster processor, faster contexts switching, faster higher resolution ADCs, higher resolution PWMs, programmable gain amplifiers, live flash update, and consume less power.
In all, there are 14 members of the family, including the smallest ever GS dsPIC – in a 4x4mm (28pin) package.
To help analogue PSU designers switch to digital-in-the-loop, the firm has also released a digital compensation design tool for calculating loop parameters (more about this later), and a series of design workshops.
Arranged with Biricha Digital, the workshops are also intended for established firmware designers who are unfamiliar with power supplies.
Faster processor and context switch
Processor clock frequency is 40% up in generation three, from 50Mips to 70Mips.
This just allows the core to keep up with higher power switching frequencies, and also provides headroom for more complex control and frequency compensation algorithms, said Microchip marketing manager Tom Spohrer, pointing out that algorithms are increasingly adaptive, non-linear and predictive in nature (see below). And extra processing power means room for customer-specific functions such as fault logging and intelligent fan control.
Digital-in-the-loop requires a repeating sequence of output measurement via ADC, calculations based on these measurements, and consequent modification of the output PWM setting.
A fundamental limitation on the agility of a digital power supply is the delay from ADC initiation to PWM modification.
Part of this delay is reduced by quickly executing algorithms, and part is dependent on interrupt response speed.
Analysis of code used with earlier GS PICs has revealed that half the time within interrupt service routines (ISRs) is spent saving registers, according to Spohrer.
To cut this delay, two sets of shadow ‘context’ registers have been implemented behind the main register set in gen-3 devices. This removes all need to save the state of individual registers during ISRs, and allows interrupt data to persist between interrupts. Having two sets of context registers allows two different levels of interrupt to have their own persistent data.
Overall, said Spohrer, ISR latency has been halved.
Faster core, context registers, and ADC changes described below have increased maximum possible power switching frequency.
“With the old GS, 500kHz power switching was theoretically possible and I have seen it at well over 300kHz,” said Spohrer. “With the new one, certainly 500kHz switching frequency will not be a problem.”
Faster higher resolution ADCs
There are now five 12-bit analogue-to-digital converters (ADCs) which convert in 300ns, compared with 10bit 600ns ADCs in gen-two. Total throughput is now 16Msample/s.
Depending on variant, the ADCs are wired to a maximum total of 22 analogue inputs, and each of these 22 inputs now has its own results register to save the core maintaining a ADC/input list.
For resolution up to 16bits, the ADCs can be run slower – 200ksample/s is possible at 14bit resolution, for example.
“16bit resolution is not fast enough for loop control, but it is great for power measurement. 12bit was on the hairy edge for power measurement,” said Spohrer.
To further cut latency, ADCs now send interrupts early – predictably before the conversion is complete.
At the other end of the control loop, there are 10 channels of PWM in five pairs, now with 1ns resolution.
According to Microchip figures, from ADC start-conversion to PWM update, running a three-pole three-zero (3P3Z) compensator algorithm, the new GS takes 890ns compared with 1.84µs on gen-two silicon.
Second and third-generation GS timing compared
There are up to four voltage comparators for sensing analogue quantities, each with a 12bit DAC to set the level of its reference input.
Used for fault detection, the comparators can be routed through to the PWMs, shutting down the switching outputs within 15ns without core intervention.
For sensing small signals, two programmable gain (4 to 64x) amplifiers have been added. They are fairly fast, with a 40MHz gain bandwidth product.
Live flash update
Some customers, particularly server PSU makers, have been asking for a live firmware update capability.
“Customers couldn’t tell us what they wanted to change, and they were not very forthcoming on what they changed in the past, but they wanted it,” said Spohrer.
In response, the firm has implemented dual flash partitions in 64kbyte variants, plus an instruction in the core to swap to new addresses.
To prove the scheme works even in extreme conditions, Microchip demonstrated swapping compensation schemes back and forth from 2P2Z to 3P3Z (see below), cleanly within one ADC-PWM loop control cycle, without upsetting analogue fault detection.
“This means you can change compensator parameters in real time, although I am not sure why you would want to,” said Spohrer. “More likely you would want to add a new command to a PMbus stack.”
Security on updates, he added, can be run in software in the background as there is no speed restriction on loading new code, only swapping it in once it has been loaded and verified.
Less power
According to Microchip, third generation GS chips consume 80% less than earlier counterparts, increasing efficiency of a hypothetical 100W eighth brick dc/dc converter by 0.26%, cutting 4% from its power dissipation, and reducing the size of the chip’s own power supply.
The starter kit implements separate buck and boost converters, and features hardware slope compensation for peak current mode operation. Resistors on the back can be switched in as output loads
The compensation calculator tool Microchip is offering works in conjunction with the compensation library released last year.
It generates header files with compensator coefficients and will calculate parameters for five compensation schemes: 2P2Z, 3P3Z, PID (proportional-integral-derivative), Type II and Type III.
Data can be fed in as a polynomial, poles and zeros, or from tables created by network analysis or simulation.
According to Spohrer, PID schemes are hardly seen anymore, and loops are more likely to be 2P2Z for current and 3P3Z for voltage.
Why digital power?
Mostly the need for digital power comes from the need to maintain high efficiency over a wide load range, said Spohrer: “I’d venture it’s impossible to achieve 90% efficiency at 10% load and 96% maximum efficiency in a practical power supply with analogue control.”
Digital control makes such supplies possible by reducing the number of hardware components needed to implement the necessary adaptive algorithms.
Beyond this, digital control allows non-linear and predictive algorithms to be implemented to improve dynamic response to transients, and allows detailed improvements to be added – such as adjusting dead-time depending on instantaneous load.
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