SDAccel environment
The most aggressive efforts of microprocessor vendors to shrink feature sizes, move to new FinFET processes, and add special power-saving states to CPUs, have not been enough to deliver the performance and power requirements of an increasing number of applications which are handling large amounts of data at increasingly high throughput rates.
It has been known for some time that programmable hardware in the form of FPGAs, in conjunction with a host processor can deliver up to 25x better performance/watt than microprocessors in these applications.
For example, FPGAs can be used as co-processing accelerators for data centre, medical and HPC computer acceleration and companies such as Baidu (DNN prediction for search), Dell (image resizing) and Microsoft (Bing search) have shown that FPGAs can deliver the much required acceleration at their performance/watt targets.
However, this technology has not been directly accessible to software developers until recently.
With Simulink from MathWorks and LabView from National Instruments supporting a combination of software, model, platform, and IP-based design environments since September 2013, Xilinx has recently added SDNet and SDAccel to its portfolio, the first two products in the SDx family of “Softly Defined” development environments for systems and software engineers.
SDx allows developers with little or no FPGA expertise to use high level programming languages to leverage the power of programmable hardware with industry standard processors on or off chip.
The key to this technology has been creating highly optimised hardware from C-based design, IP based tools and high performance implementation tools. Xilinx has been able to mature the various technologies for nearly a decade to provide software development environments for OpenCL, C and C++.
The SDAccel development environment for OpenCL, C, and C++, enables up to 25x better performance/watt for CPU-based systems in data centres, medical and high performance computing systems.
The SDNet environment supports SDN functionality while also allowing for differentiation through software programmable data plane hardware with content intelligence that dynamically collaborates with control plane SW while addressing the performance, flexibility, and security challenges of modern content-oriented networking.
We anticipate a growing acceptance of OpenCL by CPU/GPU vendors, server OEMs, and data-centre managers alike as more parties recognise that C-based optimising compilers for single processor architectures can only offer small reductions in overall power dissipation within the server rack.
This has been evident for some time in applications that make heavy use of DSP and graphics, such as data mining and intelligence, 3D visualisation, and parallel algorithm exploitation in microbiology, financial trading, and similar vertical markets.
The broad-based server OEM effort to make heavier use of FPGAs in data centres, however, is an indication that the need for higher integration and lower power in heterogeneous computing is extending to more general-purpose applications such as search-engine queries and Hadoop queries.
Writer is Giles Peckham, regional marketing director, Americas & EMEA, Xilinx
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