Renesas to use RISC-V cores in ASSPs

Renesas has chosen the AndesCore IP 32-bit RISC-V CPU cores to embed into ASSPs that will begin customer sampling in the second half of 2021. “Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA for SoCs,” says  Frankwell Lin, President of Andes, “it marks the ...

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