SiFive adds Risc-V micro-instruction cache for slow memories

SiFive has added a ‘micro instruction cache’ option to its Risc-V e2 core – the smallest of its Risc-V intellectual property offerings. Introduced in release 19.05, the micro instruction cache (see μ$ for cache in diagram) sits between the instruction fetch port and the memory system, and offers a speed-up in execution when operating from ...

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