Cadence Design Systems has announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET process. Cadence and TSMC are also continuing to collaborate on the advancement of 7nm technologies and have completed tools certification and the delivery of the latest Process Design Kit (PDK) for mutual customers to initiate early design starts based on the most current version of the DRM and SPICE model.
from DIGITIMES: IT news from Asia http://ift.tt/1M9EKTy
via Yuichun
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