Chips at risk from bad voltages, says Mentor

Electrical reliability and protection from electrostatic discharge (ESD) has become more important to IC designers as on-chip geometries shrink and device complex increases.

ESD is not a new phenomenon in chip design but its importance to IC designers has increased in recent years.

The main factors for this are:

·         Smaller on chip geometries for wiring as well as feature size.

·         Multiple power islands on the one chip

·         Designing in third-party silicon IP

“The big risk designers have is from allowing inappropriate voltages being applied to different parts of the circuit on the same die,” says Carey Robertson, product marketing director at Mentor Graphics.

Chip reliability is also enforced by industry standards such as the ISO26262 automotive device certification.

This puts greater pressure on the chip designer to check for issue such as electrical overstress, over-heating and latch-up at all stages of the design.

“This means designers must ensure the longevity of devices especially if they are being designed into applications such as automotive or medical,” says Robertson.

So what does the designer need to think about?

·         Current density limits for specific areas of the die

·         Identifying power islands within the design

·         Pad spacing

·         Bond wire widths

·         Resistance matching

Foundries have their own reliability check. For example TSMC will give designers an ESD/latch-up design kit with as many as 60 design rule checks for 28nm devices and below.

For many designers this could be a new task for them, and the EDA firms have now introduced tools which can automate the process to a great extent.

Mentor’s tool for performing ESD and multiple power domain checks is called Calibre PERC.

According to Robertson, geometrical and electrical verification requirements must be described by a topological view rather than single device/pin to net relation.

“The tool can give a topological view incorporating many layout-related parameters as well as circuitry-dependent checks,” says Robertson.

According to Robertson, there will be an inevitable increase in the design cycle runtime, but he says this can be typically “a matter of hours”.

Designers will have to budget for this, because this is a world where customers are increasingly looking for device longevity as well as performance and low cost.

 

Richard Wilson

from News http://ift.tt/1JA53zd
via Yuichun